The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a shallow trench device isolation (STI) structure and a fabrication process thereof.
In semiconductor integrated circuit devices, a so-called device isolation structure is used for isolating a plurality of device regions formed on a common semiconductor substrate from each other electrically.
In conventional semiconductor integrated circuit devices, a field oxide film formed by a so-called LOCOS process has been used for such a device isolation structure. On the other hand, a field oxide film has a tendency of having an increased area as compared with an area of a device region due to the formation of bird""s beak structure that penetrates into the device region and is problematic in view of miniaturization of semiconductor integrated circuit device. Thus, recent semiconductor integrated circuit devices using semiconductor devices of sub-micron size or sub-half-micron size tend to use less area-occupying shallow-trench device isolation (STI) structures, in place of conventional field oxide films.
FIG. 1 shows the construction of a semiconductor device 10 having an STI structure according to a related art of the present invention.
Referring to FIG. 1, the semiconductor device 10 is formed on a device region defined on a p-type Si substrate 11 by a device isolation region 12 having the STI structure, and n-type diffusion regions 11a-11c having an LDD structure are formed in the Si substrate 11 in correspondence to the device region. The device region is further covered by a gate oxide film 13 and a gate electrode 14A of a first MOS transistor is formed on the gate oxide film 13 in correspondence to the channel region between the diffusion regions 11a and 11b. Further, a gate electrode 14B of a second MOS transistor is formed in correspondence to the channel region between the diffusion regions 11b and 11c. 
Each of the gate electrodes 14A and 14B is covered by a pair of sidewall oxide films and further by an interlayer insulation film 15. Further, the interlayer insulation film 15 is formed with contact holes 15A-15C respectively exposing the diffusion regions 11a-11c, and the contact holes 15A-15C are filled by polysilicon electrodes 16A-16C, respectively.
As can be seen from FIG. 1, the device isolation region 12 of the STI structure is formed of device isolation trenches 11A and 11B each formed in the Si substrate 11 and an SiO2 film filling the device isolation trenches 11A and 11B and forming the region 12. Thus, the device isolation region 12 does not form a bird""s beak structure and the area of the device isolation region can be minimized.
FIG. 2 shows the cross section of the semiconductor device 10 of FIG. 1 taken in a direction perpendicular to the cross-section of FIG. 1 taken along the gate electrode 14A. In FIG. 2, the representation of the interlayer insulation film 15 or the electrodes 16A and 16B is omitted. Further, the illustration of the sidewall oxide film of the gate electrode 14A is omitted.
Referring to FIG. 2, the SiO2 film forming the STI structure is formed with a depression along the boundary to the Si substrate 11 associated with the etching of a pad oxide film on the Si substrate 11, and it can be seen that the SiO2 film forms an edge having an acute angle in such a depression. As a result of the existence of such an edge of acute angle, there is caused a concentration of electric field in the SiO2 film when a gate voltage is applied to the gate electrode 14A and there arises a problem that the threshold voltage of the MOS transistor having the gate electrode 14A is reduced effectively in the vicinity of the edge of the acute angle.
When such a decrease of the effective threshold voltage is caused, the MOS transistor starts to conduct at a gate voltage below the desired threshold voltage as represented in the drain current Idxe2x80x94gate voltage Vg characteristic curve of FIG. 3, and there appears a kink in the characteristic curve in which the drain current increases sharply with the increase of the gate voltage.
Further, in such a structure, due to the formation of the depression in the SiO2 film 12, there can be a case, when forming the gate electrode 14A or 14B by patterning a polysilicon or amorphous silicon, in that an etching residue of polysilicon or amorphous silicon remains in such a depression and causes problems such as short circuit.
In order to avoid the kink of the characteristic curve caused by the electric field concentration in the edge part of the STI structure, there is proposed an STI structure formed according to the process of FIGS. 4A-4D in another related art of the present invention.
Referring to FIG. 4A, an initial oxide film 23 and a hand mask layer 24 of an SiN film are formed consecutively on a Si substrate 21 and an SiO2 film 25 is formed further on the SiN film 24 by a high-temperature CVD process. Further, an opening 26 is formed through the films 23-25 so as to expose the Si substrate 21.
Next, in the step of FIG. 4B, the structure of FIG. 4A is oxidized in a wet atmosphere and a minute LOCOS 27 is formed in correspondence to the opening 26. Further, a sidewall oxide film 25A is formed on the sidewall of the opening 26.
Further, in the step of FIG. 4C, the minute LOCOS 27 is subjected to a dry etching process while using the SiN film 24 and the sidewall oxide film 25A as a mask, to form a trench 21A so as to reach the Si substrate 21. Further, the trench 21A is filled with an SiO2 film and subsequently applied with an etch back process, and the SiN film 24 is removed. Further, a sidewall oxide film 28A is formed outside the SiO2 film thus formed, as represented in FIG. 4D.
In such an STI structure, no edge part having an acute angle is formed between the Si substrate 21 and the trench 21A and the problem of decrease of the threshold voltage of the MOS transistor caused by concentration of electric field is avoided.
However, the STI structure having such a construction requires a complex fabricating process and increases the cost of fabrication.
In a further related art of the present invention, there is proposed an STI structure that avoids the problem of electric field concentration with a simpler construction as represented in FIG. 5.
Referring to FIG. 5, a trench 31A is formed in an Si substrate 31 and the trench 31A is filled with an SiO2 film 32. Further, sidewall insulation films 33 are formed at both lateral sides of a projecting part of the SiO2 film 32 on the substrate 31 by a deposition and etch-back of an SiO2 film.
The foregoing process, while being able to form the STI structure by a simple process, has a drawback in that the surface of the Si substrate 31 tends to be contaminated by impurities in relation to the etch-back process of the SiO2 film.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having an STI structure and is capable of avoiding the concentration of electric field at the edge part of the STI structure effectively and a fabrication process thereof.
Another object of the present invention is to provide a semiconductor device, comprising:
a substrate; and
a device isolation structure formed on said substrate for defining a device region,
said device isolation structure comprising:
a trench formed in said substrate; and
an insulating film filling said trench,
said insulating film including an extension part extending outwardly from an outer edge of said trench on a surface of said substrate, and a projecting part projecting upwardly from said extension part in correspondence to said outer edge of said trench.
Another object of the present invention is to provide a method of fabricating a semiconductor device having a shallow trench device isolation structure, comprising the steps of:
forming a first oxide film on a Si substrate;
forming a polishing stopper layer on said first oxide film;
forming a trench through said polishing stopper layer and further through said first oxide film such that said trench reaches said Si substrate;
etching said first oxide film exposed at said trench to as to cause a recession in a sidewall surface of said first oxide film with respect to a sidewall surface of said trench, such that there is formed a space between a top surface of said Si substrate and a bottom surface of said polishing stopper layer such that said space is opened at said sidewall of said trench;
oxidizing said sidewall surface and a bottom surface of said trench to form a second oxide film such that said second oxide film covers said top surface of said Si substrate exposed by said space in continuation with said first oxide film;
depositing a Si film on said polishing stopper layer such that said Si film covers said second oxide film and such that said Si film fills said space;
depositing a third oxide film on said Si film so as to fill said trench;
removing said third oxide film and said Si film underlying said third oxide film by a chemical mechanical polishing process while using said polishing stopper layer as a stopper;
removing said polishing stopper layer and said first oxide film from said top surface of said Si substrate; and
oxidizing said Si film.
Another object of the present invention is to provide a method of fabricating a semiconductor device having a shallow trench device isolation structure, comprising the steps of:
forming a first oxide film on a Si substrate;
forming a polishing stopper layer on said first oxide film;
forming a trench through said polishing stopper layer and further through said first oxide film underneath said polishing stopper layer such that said trench reaches said Si substrate;
etching said first oxide film exposed at said trench so as to cause a recession of a sidewall surface of said first oxide film with respect to a sidewall surface of said trench, such that there is formed a space between a top surface of said Si substrate and a bottom surface of said polishing stopper such that said space is opened at said sidewall surface of said trench;
oxidizing said sidewall surface and a bottom surface of said trench to form a second oxide film such that said second oxide film covers said sidewall surface and said bottom surface of said trench and said top surface of said Si substrate exposed by said space in continuation with said first oxide surface;
forming a Si film in said trench such that said Si film fills said space;
depositing a third oxide film so as to fill said trench;
removing said third oxide film by a chemical mechanical polishing process while using said polishing layer as a stopper;
removing said polishing stopper layer and said first oxide film from said top surface of said Si substrate; and
oxidizing said Si film.
Another object of the present invention is to provide a method of fabricating a semiconductor device comprising a device isolation trench formed in a substrate and an insulating film filling said device isolation trench, comprising the steps of:
causing a recession in an oxide film formed on a surface of said substrate with regard to a sidewall surface of said device isolation trench at an edge of said device isolation trench, to form a space;
forming a Si film so as to fill said space;
removing said oxide film from said surface of said substrate while leaving said Si film;
filling said trench by an oxide film; and
oxidizing said Si film to form an oxide film as a part of said oxide film.
Another object of the present invention is to provide a method of forming a device isolation structure comprising a device isolation trench formed in a substrate and an insulating film filling said device isolation trench, said method comprising the steps of:
causing a recession in an oxide film formed on a surface of said substrate with respect to a sidewall surface of said device isolation trench at an edge of said device isolation trench, to form a space;
forming a Si film so as to fill said space;
removing said oxide film from said top surface of said substrate while leaving said Si film;
filling said trench by an oxide film; and
oxidizing said Si film to form an oxide film as a part of said oxide film.
According to the present invention, in a semiconductor device having an STI structure, the device isolation trench constituting the STI structure is filled by an SiO2 film such that the SiO2 film extends over the surface of the substrate to an outer side of the device isolation trench and such that the SiO2 film projects slightly in the upward direction from the substrate surface. By doing so, no acute angle part is formed in the SiO2 film. Thus, there occurs no electric field concentration in the SiO2 film even when a gate electrode extends over the SiO2 film and the problem of change of the threshold voltage is avoided. Further, the present invention does not include a dry etching process for etching back the substrate surface, and thus, there occurs no problem of contamination of the substrate surface by impurities. Further, the SiO2 film has an upwardly convex shape in the device isolation trench, and the problem of residue formation of polysilicon pattern or amorphous silicon pattern in the depressed part of the SiO2 film, which tends to appear in a conventional STI structure, is eliminated.